eSPI – New, Cost Effective and Higher Performance Design Standards for LPC Peripherals and Other Devices

Leading the industry to improve data transactions with less power and lower cost, Intel is defining the eSPI standard, which many manufacturers – at the chip, board and system levels – are integrating in their products.

The eSPI (enhanced serial peripheral interface) is a serial bus that is based on SPI. The features include a four-wire interface (receive, transmit, clock and slave select) and three configurations:

  • Single IO (or standard IO): Clock, Chip-select, Uni-directional data signal (MOSI), Uni-directional data signal (MISO)
  • DUAL IO: Clock, Chip-select, Bi-directional data signal (IO0), Bi-directional data signal (IO1)
  • QUAD IO: Clock, Chip-select, Bi-directional data signal (IO0), Bi-directional data signal (IO1), Bi-directional data signal (IO0=2), Bi-directional data signal (IO3)

The technical advancements include lower voltage signal levels (1.8V vs. 3.3V), lower pin count, and the frequency is twice as fast (66MHz vs. 33MHz). Because of its enhancements, the eSPI is expected to replace the LPC (lower pin count) interface. LPC has been utilized in the computing market over 15 years. It is definitely time to reset the standards for today’s market demands and performance requirements.

  • The lower signal level reduces the power needed. It also inhibits the signal noise that often occurs with higher clock speeds.
  • The reduced pin count decreases the number of traces needed on the circuit board. eSPI requires a maximum of 8 pins  for one slave: chip select, clock, 4 data lines, alert (optional) and  reset.
  • The accelerated clock rate enables more bandwidth for data transfer and faster operations: 4x 66 MHz.
  • To comply with product requirements, system designers can choose the maximum clock rate to support: 20, 25, 33, 50 or 66 MHz.

With the stability of a defined industry-wide standard, the eSPI can support the future development of  client and server platforms, including the peripherals and memory, for  many years. Together, Figure 1 and Figure 2 show one example of how system designs can evolve.

Figure 1 shows an example of an SPI host chipset.

 Example of SPI chipset design for LPC peripherals
Figure 1: Host Chipset with the SPI Bus   (source:

Figure 2 shows an example of an eSPI host chipset and how the pin count is reduced. This example supports both SPI and eSPI devices.

Example of eSPI chipset design for LPC peripherals
Figure 2: Host Chipset with the eSPI Bus      (source:

Intel’s Enhanced Serial Peripheral Interface (eSPI) specification shows many example usages of eSPI.

Whether you are using released or proprietary devices,  proving the concept or production testing your projects, Total Phase provides high performance, cost effective tools for the development, test and simulation. For eSPI designs, look into our Promira Serial Platform and our eSPI Analysis Application. Please contact us at if you would like to learn more about how our tools can make your projects easier.

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