Troubleshooting Unexpected MISO Data from an Aardvark SPI Slave
I am using the Total Phase Aardvark I2C/SPI Host Adapter as an SPI slave to receive and transmit data with an FPGA in an SPI digital system. I observed the following behaviors:
- FPGA SPI master sends [0x1 0x1 0x1 0x1] on MOSI
- Aardvark SPI slave receives [0x1 0x1 0x1 0x1] on MOSI
- Aardvark SPI slave sends [0xFF 0xFE 0xFD 0xFC] on MISO
- FPGA SPI master receives [0xFF 0x1 0x1 0x1] on MISO
Connecting a scope to the FPGA SPI master interface, I see MISO is being toggled as [0xFF 0x1 0x1 0x1], despite the Aardvark SPI slave sending [0x1 0x1 0x1 0x1] correctly.
What causes this behavior? Is the Aardvark SPI slave transmitting the first byte correctly, but the remaining (n-1) bytes being the FPGA SPI master's own transmitted bytes on the MISO?
Response from Technical Support:Thank you for your question! It’s important to first confirm that the clock edges are aligned and that the clock starts at the correct idle polarity. If the master and slave disagree on either, data transfer errors can occur. Details of edge mode and other factors are covered in the following sections.
Setting Edge Mode to Transmit SPI Data
The master and slave must agree about the data frame for the exchange. To do so, ensure the SPI master and the slave chipset are operating at the same mode.
The following describes the method by which each mode of SPI (0,1,2,3) can be mapped by checking how the data is sampled by referring to the above diagram simultaneously:
- At CPOL=0 the base value of the clock is zero, i.e. the idle state is 0 and active state is 1.
- For CPHA=0, data is captured on the clock's rising edge (low-to-high clock transition) and data is output on a falling edge (high-to-low clock transition).
- For CPHA=1, data is captured on the clock's falling edge and data is output on a rising edge.
- At CPOL=1 the base value of the clock is one (inversion of CPOL=0), i.e. the idle state is 1 and active state is 0.
- For CPHA=0, data is captured on clock's falling edge and data is output on a rising edge.
- For CPHA=1, data is captured on clock's rising edge and data is output on a falling edge.
Data Sampling
- When CPHA=0, sampling occurs on the first clock edge; data is transmitted on the active to idle state. NOTE: with CPHA=0, the data must be stable for a half cycle before the first clock cycle.
- When CPHA=1, sampling on the second clock edge, regardless of whether that clock edge is rising or falling; data is transmitted on the idle to active state.
If transmission occurs on a particular edge, then capturing occurs on the opposite edge. For example, when transmission occurs on the falling edge, then reception occurs on the rising edge, and vice versa.
MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next clock transition. SPI master and slave devices will sample data at different points during that half cycle.
For more information, refer to SPI Modes in the Aardvark I2C/SPI Host Adapter User Manual.
SPI Slave Inter-Byte Timing Requirements
If data errors occur when the edges are set correctly, the issue may be missing required inter-byte delays.
The Aardvark SPI slave can operate at any bitrate up to 4 MHz. However, for correct transmission from slave to master there must be at least 4 µs delay between the end of byte n and start of byte n+1 for the MISO data to be setup properly for byte n+1. Otherwise, the Aardvark adapter will simply return the data it just received. Likewise, for correct reception of data by the slave, there must be at least 10 µs between the start of byte n and the start of byte n+1.
For more information, refer this Knowledge Base article about SPI timing requirements when communicating with an SPI slave device.
We hope this answers your questions. Additional resources that you may find helpful include the following:
If you want more information, feel free to contact us with your questions, or request a demo that applies to your application.