How are CPOL, CPHA and Bitrate Configured for a Host Adapter that is in SPI Slave Mode?

Question from the Customer:

How critical is the bitrate setting in SPI Slave mode? Does the Aardvark I2C/SPI Host Adapter communicate only with other SPI devices that support exactly the clock speeds that the Aardvark does? If not, should the bit rate on the Aardvark be configured higher than that of the SPI master or lower?

Also, the Control Center Serial Software User Manual uses terminology such as rising/falling and sample/setup. How do those terms correlate to CPOL (clock polarity) and CPHA (clock phase), and can you provide more information about that configuration?

Response from Technical Support:

Thanks for your questions! Setting the bitrate applies only to the device in the SPI master mode; it is not necessary to set the bitrate for the device in slave mode, as SPI slave devices use the clock of the master. However, the master and slave devices must agree to the data frame, which is related to the clock transitions, polarity and phase, as indicated in section 4.2 of the Control Center Serial Software User Manual.

Configure SPI Mode via the Control Center Software Serial Figure 1: Configure SPI Mode via the Control Center Software Serial

The Aardvark adapter is capable of sending SPI data at 8 MHz, while our newest product, the Promira Serial Platform, with the SPI Active – Level 1 Application, can send data at 12.5 MHz. The Control Center Serial Software can be used with both devices.

Here are the definitions of rising/falling and sample/setup, relative to CPOL and CPHA:

  • rising/falling is equivalent to CPOL = 0; the leading edge of the clock is rising and the trailing edge is falling.
  • falling/rising is equivalent to CPOL = 1; the leading edge of the clock is falling and the trailing edge is rising.
  • sample/setup is equivalent to CPHA = 0; data is sampled on the leading edge of the clock.
  • setup/sample is equivalent to CPHA = 1; data is sampled on the trailing edge of the clock.

Based on those settings, four SPI modes are possible, which are illustrated in Figure 2 below.

The Clock Polarities and Clock Phases affect the SPI Modes Figure 2: Clock Polarities and Clock Phases of SPI Modes

For example, setting the clock polarity to CPOL=0 would configure the SPI to idle the SCLK clock line as low. The clock would then transition low-to-high on the leading edge and high-to-low on the trailing edge.

Similarly, the phase option determines whether to sample or setup on the leading edge. For example, setting the clock phase to CPHA=0 would configure the SPI to sample on the leading edge and to setup on the trailing edge.

For more information about CPOL (clock polarity) and CPHA (clock phase), please refer to section 1.2.3 of the Aardvark I2C/SPI Host Adapter User Manual. For more information about the commands that affect CPOL and CPHA, please refer to section 5.6.2 of the Aardvark I2C/SPI Host Adapter User Manual.

For more details, please refer to the following documents:

We hope this answers your questions. If you have other questions about our host adapters or other Total Phase products, feel free to email us at sales@totalphase.com, or if you already own one of our devices and have a technical question, then please submit a request for technical support.

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